SAN JOSE, Calif. — IC package design has become a huge bottleneck for getting chips out the door, but there are few automated tools that can help, according to panelists at the International Symposium ...

Santa Clara, Calif. — As chip designers, Kaushik Sheth and Egino Sarto struggled to fit silicon into cost-effective packages. Now they're trying to convince other chip designers to adopt a ...

TEMPE, AZ--(Marketwire - Oct 22, 2012) - EPEPS -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced enhancements to its Allegro ® 16.6 ...

Cadence Design Systems (News - Alert), Inc. has unveiled an enhanced version of its Allegro 16.6 Package Designer and System-in-Package offering. Discreet IC package necessities for next-generation ...

Originally, I started to write this entry about a Sustainable Brand Identity. But as I put pen to paper and fingers to keyboard, I realized that my opening paragraph deserved a bit more attention.

Members can download this article in PDF format. Today, advances in semiconductors and ICs are producing ever smaller and denser circuits. With that comes the challenge of efficiently packaging and ...